1. Field of the Invention
The present invention relates to a method of manufacturing a solid-state imaging device, particularly a method of forming a pad part for leading out an electrode in the solid-state imaging device. The present invention also relates to a method of manufacturing an electronic apparatus using such a solid-state imaging device.
2. Description of the Related Art
Among solid-state imaging devices, specifically CMOS solid-state imaging devices, backside-illuminated solid-state imaging devices have been proposed for improving photoelectric conversion efficiency and sensitivity to incident light (see Japanese Unexamined Patent Application Publication No. 2005-353631, Japanese Unexamined Patent Application Publication No. 2005-347707, and Japanese Unexamined Patent Application Publication No. 2005-363955). The backside-illuminated solid-state imaging device includes photodiodes that serve as photoelectric conversion parts on a semiconductor substrate. In addition, the device includes pixel transistors, a plurality of wiring layers, and so on, constituting a signal circuit on the front side of the semiconductor substrate, while receiving incident light from the backside thereof.
In the backside-illuminated solid-state imaging device, a pad part is provided on the backside of the semiconductor substrate to supply necessary electric potentials to the plurality of wiring layers on the front side of the semiconductor substrate. FIG. 1 is a schematic cross-sectional view of the main part of the backside-illuminated solid-state imaging device. FIG. 1 illustrates the cross section of an area on the backside of the backside-illuminated solid-state imaging device, including a pad part 60 formed on the periphery thereof.
A backside-illuminated solid-state imaging device 70 includes an imaging region and peripheral circuits on a semiconductor substrate (for example, a monocrystal silicon layer) 53. The imaging region includes a plurality of pixels each having a photodiode (PD) 54 as a photoelectric conversion part and a plurality of pixel transistors (MOS transistors). In addition, the peripheral region on the backside of the semiconductor substrate includes a pad part connected to a necessary wiring of a plurality of wiring layers, or a so-called electrode lead-out pad part 60. The pixel transistors in the pixel are formed on the surface of the semiconductor substrate 53 but not shown in the figure. Furthermore, on the front side of the semiconductor substrate 53, a plurality of wiring layers 51, which is constructed of layers of wirings 52 [521, 522, and 523], is formed on an insulating interlayer 50. In this example, a first-layer wiring 521, a second-layer wiring 522, and a third-layer wiring 523 are formed. Any of these wiring layers may be made of Cu wiring, Al wiring, or the like. At least a wiring 521a facing the pad part 60 is made of Al wiring. A supporting substrate 61, such as a silicon substrate, is adhered on the front side of the plurality of wiring layers 51 on a bonding layer 63.
On the other hand, on the backside of the semiconductor substrate 53, an insulating layer 55 as an antireflective coating, a passivation layer 56, and a planarizing film 57 that serves as a base-adhesive layer for an on-chip color filter are stacked in this order. The insulating layer 55 used as the antireflective coating is constructed of, for example, two layers, a SiN layer and a SiO2 layer, which are stacked in this order. For example, on-chip color filters 59 of red (R), green (G), and blue (B) are formed on the planarizing film 57 corresponding to pixels of the imaging region, that is, the respective photodiodes (PDs) 54. In addition, on-chip microlenses 58 are formed on the respective on-chip color filters 59.
The imaging region includes an effective pixel area, and an optical black area on the outside of the effective pixel area. The optical black area specifies the black level of a pixel. The optical black area includes the pixels and color filters as those in the effective pixel area. Although not illustrated, a light-shielding film is formed all over the surface including other pixel transistors, and the peripheral circuit section, except for each of light-sensing parts of the effective pixel area, that is, the photodiodes (PDs) 54 and the pad part 60. An opening 62 is formed in the pad part 60. The opening 62 is provided for exposing desired wiring of the plurality of wiring layers 51, the wiring 521a in this example.
FIGS. 2A and 2B illustrate an example method of forming the pad part 60. First, as shown in FIG. 2A, pixels each having a photodiode (PD) 54 and pixel transistors (not shown) are formed on a semiconductor substrate 53 and a plurality of wiring layers 51 is then formed on the front side of the semiconductor substrate 53, followed by bonding a supporting substrate 61 to the plurality of wiring layers 51 on a bonding layer 63. Furthermore, an insulating layer 55 as an antireflective coating, a passivation layer 56, and a planarizing film 57 that serves as a base-adhesive layer are stacked in this order on the backside of the semiconductor substrate 53. Subsequently, an opening 62 is formed by etching and removing the part, which corresponds to the pad part 60, of each of the planarizing film 57, the passivation layer 56, the insulating layer 55, the semiconductor substrate 53, and the insulating interlayer 50 up to the first wiring 521a of the plurality of wiring layers 51.
After that, as shown in FIG. 2B, an organic film that serves as an on-chip color filter member, such as a resist film, is formed and then patterned. As a result, on-chip color filters 59 of, for example, red (R), green (G), and blue (B) are formed. Furthermore, an organic film that serves as an on-chip microlens member 58A, such as a resist film, is formed and then subjected to a transfer method including an etch-back process to form on-chip microlenses 58.